Design of Polynomial Basis Multipliers over Gf(2)

This article addresses an efficient hardware implementations for multiplication over finite field GF(2). Multiplication in GF(2) is very commonly used in cryptography and error correcting codes. An efficient hardware could reduce the cost and development for these applications. This work presents the hardware implementation of polynomial basis. In this case, the multipliers were designed using bit-serial multiplication , bit-parallel multiplication, PCA based serial multiplication and PCA parallel based multiplication algorithms, the synthesis and simulation were carried out using Quartus II v.5.0 of Altera, and the designs were synthesized on the Stratix II EP2S60F1020C3. The simulation results show that the multipliers designed present a very good performance using small area.